Technical Field
This invention relates to integrated circuits, and more particularly, to techniques for implementing branch prediction within processors and processing cores.
Description of the Related Art
Computing systems typically include one or more processors or processing cores which are configured to execute program instructions. The program instructions may be stored in one of various locations within a computing system, such as, e.g., main memory, a hard drive, a CD-ROM, and the like. In some cases, a hierarchy of local memories or cache memories, may be employed to store frequently accessed program instructions and data.
When a processor or processing core retrieves a program instruction (commonly referred to as an “instruction fetch”), the processor or processing core issues a request via a communication bus to the device or memory where the desired program instruction is located. Each retrieved instruction may, in turn, determine the next instruction to be retrieved. Some program instructions contain conditional statements, such as, e.g., an if-then-else statement. When such an instruction is received by a processor or processing core, there are two possible sets of instructions (commonly referred to as “branches”) that the processor or processing core may fetch from. Some processors and processing cores attempt to predict how the conditional will evaluate and fetch instructions accordingly. This process is typically referred to as “branch prediction.”
Branch prediction may rely on a history of previous instructions that have been processed in order to predict the outcome of a conditional. Despite various methods and techniques, however, a predicted outcome may not be correct. In such cases, a processor or processing core may have fetched instructions that are not needed. When this occurs, the processor may discard the previously fetched instructions, and may wait while a proper set of instructions is retrieved from memory.